1. Field of the Invention
The invention relates to a caching method and a data storage system, and more particularly to a caching method and a data storage system capable of prolonging service lifetime of a cache memory.
2. Description of the Related Art
Currently, adopting solid state drives (SSDs) as caches for hard disk drive (HDD) arrays has gained popularity in datacenters because SSDs are superior in handling small and random reads that HDDs may not efficiently deal with. It has been widely accepted that utilizing NAND flash based SSDs as caches is a cost-effective approach for optimizing storage performance. However, modern 25-nm two-bit multi-level cell (MLC) NAND flashes usually have a limited endurance of about 3000 program/erase (P/E) cycles, which is too low to sustain on-line transaction processing (OLTP) workloads, such as Transaction Processing Performance Council-C (TPC-C) workloads. TPC-C can cause an SSD cache to be programmed and erased 39 cycles per day on average. That means, the service lifetime of SSD caches using such MLC NAND flashes is as short as about 77
  (            3000      39        ≈    77    )days. Therefore, to enable the adoption of MLC NAND flashes in SSD caches, it is critical to resolve the endurance issue.
The following are several conventional techniques proposed to improve the service lifetime of a flash-based memory given limited endurance:
1. Wear leveling aims at evenly spreading writes to the entire flash memory to prevent early wearout of blocks of the cache memory due to concentrated writes. Although wear leveling can ensure a reasonable service lifetime for flash devices with moderate write intensiveness, such as memory cards, USB drives and SSDs in personal computers (PCs), it is less effective on sustaining a long enough service lifetime for SSD caches given the high P/E rate of datacenter workloads.
2. A technique exploiting the property that if retention requirement for flash memory is lowered, errors due to leakage over time are reduced, named Retention Relaxation, is well suited to SSD caches in datacenters. Since datacenters operate continuously, data in SSD caches can be periodically refreshed to reduce their retention requirement. In addition, since a datacenter workload can program and erase SSD caches for up to 39 cycles per day, the data lifetime in SSD caches is expected to be shorter than a day.
3. Error correction code (ECC) strength is increased under a constant-rate constraint, which means that the ratio between data bits and parity bits of an ECC codeword has to be kept constant. For example, Dynamic Codeword Transition (DCT) is used to enlarge ECC codewords for strengthening ECCs. With increased ECC strength, flash devices can have higher endurance. FIG. 1 illustrates exemplary compositions of a common codeword (Ccommon) and a DCT codeword (CDCT) having the same data-to-parity ratio. The common codeword (Ccommon) has k data bits and r ECC parity bits. To increase ECC strength, the size of the DCT codeword (CDCT) is enlarged to α times that of the common codeword (Ccommon) without changing the ratio between the data bits and the parity bits. That is, the DCT codeword (CDCT) has αk data bits and αr ECC parity bits.
FIG. 2 shows an experimental result that illustrates the relationships between available cache capacity and achievable P/E cycles of a tested cache memory for different scenarios using the above conventional techniques. In this experiment, the tested cache memory is a modern 25-nm two-bit MLC NAND flash memory, and all the scenarios support wear leveling and basic ECC strength (24-bit error correction per 1080 bytes). The first scenario achieves 3 k P/E cycles, as indicated by the curve (P1) in FIG. 2. The second scenario further adopts Retention Relaxation, and achieves 14 k P/E cycles, as indicated by the curve (P2) in FIG. 2. The third scenario further adopts DTC (α=4), and achieves 21 k P/E cycles, as indicated by the curve (P3) in FIG. 2.
However, improvements may still be made to the above techniques.